Power-aware scheduling of data-flow hardware circuits with symbolic control

Power-aware scheduling of data-flow hardware circuits with symbolic control

Blog Article

We devise a tool-supported framework for achieving power-efficiency of data-flowhardware circuits.Our approach relies on formal control techniques, where the goal is to compute a strategy that can be used to drive a given model so that it satisfies charcotabs a set of control objectives.More specifically, we give an algorithm that derives abstract behavioral models directly in a symbolic form from original designs described at Register-transfer Level using a Hardware Description Language, and for formulating suitable scheduling constraints and power-efficiency objectives.We show how a resulting strategy can be translated into a piece of synchronous circuit that, when paired with the biscoff spread woolworths original design, ensures the aforementioned objectives.

We illustrate and validate our approach experimentally using various hardware designs and objectives.